A predictor circuit and a delay-aware algorithm for identifying data transfer pattern on NoC-based communication networks

Rahmani, Amir Masoud Mirmahaleh Seyedeh Yasaman Hosseini

Deploying the Internet of Things and machine learning (ML)-based applications increased processing rate and data transfer between main memory and processing elements (PEs) in NoC-based communication networks, leading to memory access problems. Predicting and identifying reusable data for different tasks can reduce memory accesses and support various applications with high flexibility. Therefore, we propose a method to minimize memory access. It provides a predictor circuit to assign the address for PEs based on data buffering into task cores due to their reusability. We also present a delay-aware algorithm to investigate the initial relationship between tasks and identify a similar pattern for the mapped task graph on the various topologies. Our algorithm and predictor circuit decrease latency for determining related data to tasks and transfers data from global buffer onto PEs and buffers them according to its reusability for tasks with similar patterns. We utilized real data of the reported COVID-19 statistics and particulate matter 2.5 (PM2.5) condensation for evaluating our method. Simulation results demonstrate reducing energy consumption, delay, memory access, and increasing area consumption by approximately 61.83%, 39.96%, 66.66%, and 0.13%, respectively, for the mapped task graphs on a mesh network before employing the circuit and algorithm.